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==Performance== The original Duron processors were derived from AMD's mainstream ''Athlon'' [[Athlon#Athlon Thunderbird|Thunderbird]] processors, the primary difference being a reduction in L2 cache size to 64 [[Binary prefix|KB]] from the Athlon's 256 KB.<ref>{{Cite web |date=2010-03-28 |title=AMD Duron - (Page 2 of 3) - The Processor Emporium (UK) |url=http://www.zen26266.zen.co.uk/Duron-2.htm |archive-url=https://web.archive.org/web/20100328014838/http://www.zen26266.zen.co.uk/Duron-2.htm |archive-date=2010-03-28 |access-date=2024-10-10 |website=Processor Emporium}}</ref> This was a relatively severe reduction, making it even smaller than the 128 KB L2 available on Intel's competing budget [[Celeron]] line. However, the originating Thunderbird architecture already featured one of the largest L1 caches at 128 KB (which was not reduced in the Duron) and also introduced AMD's switch to an exclusive cache design which effectively unified the L1 and L2 caches. Because of this, the Duron behaved as if it had a high speed 128 KB cache combined with a somewhat slower 64 KB segment giving an effective 192 KB cache, versus the traditional inclusive cache design where the L2 cache had to store a duplicate of the data stored in the L1 cache. As a comparison the inclusive design of the Celeron effectively reduced the available size of the Level 2 cache by the size of the Level 1, which resulted in an effective size of 96 KB (128-32) in contrast to the Duron's exclusive design (128+64=192). Consequently, the Duron inherited the Thunderbird's reduction in sensitivity to L2 cache size, allowing AMD to make their L2 cache higher latency and lower bandwidth to lessen processor complexity and allow better manufacturing [[Semiconductor device fabrication#Device test|yields]] without incurring a significant performance loss. The net result was that the budget Duron "Spitfire" CPU was roughly only 10% slower than an equivalently clocked (and significantly more expensive) Athlon "Thunderbird".
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