Editing Direct memory access (section)

== Principles==

=== Third-party===
[[File:NeXTcube motherboard.jpg|thumb|[[Motherboard]] of a [[NeXTcube]] computer (1990). The two large [[integrated circuit]]s below the middle of the image are the DMA controller (l.) and - unusual - an extra dedicated DMA controller (r.) for the [[magneto-optical disc]] used instead of a [[hard disk drive]] in the first series of this computer model.]]
Standard DMA, also called third-party DMA, uses a DMA controller. A DMA controller can generate [[memory address]]es and initiate memory read or write cycles. It contains several [[hardware register]]s that can be written and read by the CPU. These include a memory address register, a byte count register, and one or more control registers. Depending on what features the DMA controller provides, these control registers might specify some combination of the source, the destination, the direction of the transfer (reading from the I/O device or writing to the I/O device), the size of the transfer unit, and/or the number of bytes to transfer in one burst.<ref name=Osborne80>{{cite book |first=Adam |last=Osborne |title=An Introduction to Microcomputers: Volume 1: Basic Concepts |edition=2nd |publisher=Osborne McGraw Hill |year=1980 |isbn=0931988349 |pages=[https://archive.org/details/introductiontomi00adam/page/5 5–64 through 5–93] |url=https://archive.org/details/introductiontomi00adam/page/5 }}</ref>

To carry out an input, output or memory-to-memory operation, the host processor initializes the DMA controller with a count of the number of [[word (computer architecture)|words]] to transfer, and the memory address to use. The CPU then commands the peripheral device to initiate a data transfer. The DMA controller then provides addresses and read/write control lines to the system memory. Each time a byte of data is ready to be transferred between the peripheral device and memory, the DMA controller increments its internal address register until the full block of data is transferred.

Some examples of buses using third-party DMA are [[Parallel ATA|PATA]], [[USB]] (before [[USB4]]), and [[SATA]]; however, their [[host controller]]s use [[bus mastering]].{{cn|date=July 2024}}

=== Bus mastering ===
In a [[bus mastering]] system, also known as a first-party DMA system, the CPU and peripherals can each be granted control of the memory bus.  Where a peripheral can become a bus master, it can directly write to system memory without the involvement of the CPU, providing memory address and control signals as required. Some measures must be provided to put the processor into a hold condition so that bus contention does not occur.