Editing Counter (digital) (section)

==Characteristics==

An [[electronics|electronic]] counter is a [[sequential logic]] circuit that has a clock input signal and a group of output signals that represent an integer "count" value. Upon each qualified clock edge, the circuit will increment (or decrement, depending on circuit design) the stored count. When the count reaches the end of the counting sequence (maximum count when incrementing; zero count when decrementing), the next clock will cause the count to overflow or underflow and the counting sequence will start over.

===Signals===
[[File:Digital counter signals.jpg|thumb|Common signals on digital counters]]
Every counter has a fundamental group of signals common to state machines:
* Clock (input) - triggers state change upon rising or falling edge (known as the ''active edge''<ref name="Keslin">{{cite book |last1=Keslin |first1=Hubert |title=Top-down Digital VLSI Design: From Architectures to Gate-Level Circuits and FPGAs |date=2014 |publisher=Morgan Kaufmann |isbn=0128007729}}</ref>). 
* Reset (input) – sets count to zero. Some IC manufacturers name this signal "clear" or "master reset (MR)". Depending on the counter design, this signal may be asynchronous or synchronous.
* Count (output) - bit vector representing the accumulated count. Depending on the counter design, this may be the current state (flip-flop outputs) or an encoding of the current state.

In addition to Clock and Reset, many counters provide other input signals such as:
* Enable – allows or inhibits counting. Sometimes this is labeled ''CE'' (count enable).
* Direction – determines whether count will increment or decrement.
* Data – parallel input data which represents a particular count value.
* Load – copies parallel input data to the counter. This typically takes precedence over Enable if both Load and Enable are asserted.<ref name="AMD"/>

Counter inputs are in many cases synchronous, meaning that they only affect counter operation upon active clock edges. For any particular counter, each synchronous input signal must satisfy the setup and hold times required for proper operation (i.e., it must be stable before and after active every clock edge for specified minimum times).<ref name="Keslin"/>

Some counters provide a Terminal Count output which indicates that the next clock will cause overflow or underflow. This is used in various ways, including:

* to implement [[Counter (digital)#Cascading|counter cascading]] (combining two or more counters to create a single, larger counter) by connecting the Terminal Count output of one counter to the Enable input of the next counter.
* to dynamically change the counter modulus, by connecting Terminal Count to the counter’s Load input and applying an appropriate value to the Data inputs.

===Output encoding===

As it counts, every counter produces a sequence of output codes (bit patterns) on its Count outputs. Many of these code sequences, either by design or due to the nature of the counter, conform to widely used encoding systems. Several types of output encoding are commonly used in counters, including binary, BCD, Gray code, and one-hot.

===Modulus===

The ''modulus'' of a counter is the number of states in its count sequence.<ref name="AMD"/> A counter that has modulus value ''n'' is commonly referred to as a ''modulo-n'' or ''MOD-n'' counter. For example, a '''decade counter''' is a digital counter which has ten states, and therefore is a MOD-10 counter.<ref name="Maini">{{cite book |last1=Maini |first1=Anil K. |title=Digital Electronics: Principles, Devices and Applications |date=2007 |publisher=John Wiley & Sons, Ltd. |isbn=978-0-470-03214-5 |url=http://ebook.pldworld.com/_eBook/FPGA%EF%BC%8FHDL/-Examples-/counters%20and%20shift%20registers.pdf |access-date=1 May 2025}}</ref>

The maximum possible modulus of a counter is determined by the number of flip-flops. More specifically, a counter with ''n'' flip-flops has a maximum possible modulus of {{math|2<sup>''n''</sup>}}.<ref name="Maini" /> For example, a four-bit counter can have a modulus of up to 16 ({{math|2<sup>4</sup>}}).

Some counters (e.g., binary counters) include all possible states in their count sequences. Other counters omit one or more possible states from their counting sequences. For example, a MOD-10 (decade) counter with four flip-flops only uses ten of 16 possible states.

===Synchronous vs. asynchronous (ripple) <span class="anchor" id="Ripple counter"></span>===

Counters are broadly categorized as either synchronous or asynchronous.

In synchronous counters, all flip-flops share a common clock and change state at the same time.<ref name="Keslin"/>

In an asynchronous counter, also known as a '''ripple counter''',<ref name="Maini" /> each flip-flop has a unique clock, and the flip-flop states change at different times. Each flip-flop introduces a delay from input clock edge to output toggle. This causes the counter bits to change at different times, thus producing a ripple effect and making the count unstable as the counter input clock propagates through the circuit. The duration of this instability (the output settling time) is proportional to the number of flip-flops. This makes ripple counters unsuitable for use in [[synchronous circuit]]s that require the counter to have a fast output settling time.<ref name="Gorla">{{cite web |last1=Gorla |first1=Raju |title=Counters - Digital Circuits |url=https://vlsiweb.com/counters/ |publisher=VLSI Web |access-date=9 May 2025}}</ref> Also, it is often impractical to use ripple counter output bits as clocks for external circuits because the ripple effect causes timing skew between the bits. Ripple counters are commonly used as general-purpose counters and clock frequency dividers in applications where the instantaneous count and timing skew is unimportant. Asynchronous counters are typically not used in VLSI ICs due to the difficulties of simulating and testing them and because they require much greater design effort to ensure reliable operation.<ref name="Keslin"/>

===Count direction===

Many counters are designed to count in only one direction, meaning that they will either count up or down, but not both. A counter that only counts up is typically referred to as an ''up-counter'', and one that only counts down as a ''down-counter''.<ref name="Gorla"/>

A '''bidirectional counter''' or '''up/down counter''' is a digital counter which counts up or down as directed by a direction control input signal. In synchronous up/down counters, the control signal is a single digital input whose state indicates count direction (e.g., '1' = count up; '0' = count down). In asynchronous up/down counters the direction control may alternatively consist of two separate "up" and "down" clock inputs.