Editing Cache coherence (section)

==Overview==
In a [[Shared memory architecture|shared memory]] multiprocessor system with a separate cache memory for each processor, it is possible to have many copies of shared data: one copy in the main memory and one in the local cache of each processor that requested it. When one of the copies of data is changed, the other copies must reflect that change. Cache coherence is the discipline which ensures that the changes in the values of shared operands (data) are propagated throughout the system in a timely fashion.<ref name=":1">{{Cite book|url=http://sc.tamu.edu/systems/eos/nehalem.pdf|title=The Architecture of the Nehalem Processor and Nehalem-EP SMP Platforms|last=E. Thomadakis|first=Michael|publisher=Texas A&M University|year=2011|pages=30|url-status=dead|archive-url=https://web.archive.org/web/20140811023120/http://sc.tamu.edu/systems/eos/nehalem.pdf|archive-date=2014-08-11}}</ref>

The following are the requirements for cache coherence:<ref name=":0">{{Cite book|title=Fundamentals of parallel multicore architecture|last=Yan|first=Solihin|oclc=884540034}}</ref>
;Write Propagation: Changes to the data in any cache must be propagated to other copies (of that cache line) in the peer caches.
;Transaction Serialization: Reads/Writes to a single memory location must be seen by all processors in the same order.
Theoretically, coherence can be performed at the load/store [[granularity]]. However, in practice it is generally performed at the granularity of cache blocks.<ref name=":2">{{Cite book|title=A primer on memory consistency and cache coherence|author1=Sorin, Daniel J.|author2=Hill, Mark D.|author3=Wood, David Allen|date=2011-01-01|publisher=Morgan & Claypool Publishers|oclc=726930429}}</ref>