Editing Analog-to-digital converter (section)

==Explanation==
An ADC converts a continuous-time and continuous-amplitude [[analog signal]] to a [[discrete-time]] and discrete-amplitude [[Digital signal (signal processing)|digital signal]]. The conversion involves [[Quantization (signal processing)|quantization]] of the input, so it necessarily introduces a small amount of [[quantization error]]. Furthermore, instead of continuously performing the conversion, an ADC does the conversion periodically, [[Sampling (signal processing)|sampling]] the input, and limiting the allowable bandwidth of the input signal.

The performance of an ADC is primarily characterized by its [[Bandwidth (signal processing)|bandwidth]] and [[signal-to-noise and distortion ratio]] (SNDR). The bandwidth of an ADC is characterized primarily by its [[sampling rate]]. The SNDR of an ADC is influenced by many factors, including the [[Audio bit depth|resolution]], linearity and accuracy (how well the quantization levels match the true analog signal), [[aliasing]] and [[jitter]]. The SNDR of an ADC is often summarized in terms of its [[effective number of bits]] (ENOB), the number of bits of each measure it returns that are on average not [[Noise (signal processing)|noise]].  An ideal ADC has an ENOB equal to its resolution.  ADCs are chosen to match the bandwidth and required SNDR of the signal to be digitized.  If an ADC operates at a sampling rate greater than twice the bandwidth of the signal, then per the [[Nyquist–Shannon sampling theorem]], near-perfect reconstruction is possible. The presence of quantization error limits the SNDR of even an ideal ADC. However, if the SNDR of the ADC exceeds that of the input signal, then the effects of quantization error may be neglected, resulting in an essentially perfect digital representation of the [[bandlimited]] analog input signal.

===Resolution===
[[File:ADC voltage resolution.svg|250px|thumb|'''Fig. 1.''' An 8-level ADC coding scheme]]
The resolution of the converter indicates the number of different, i.e. discrete, values it can produce over the allowed range of analog input values. Thus a particular resolution determines the magnitude of the quantization error and therefore determines the maximum possible [[signal-to-noise ratio]] for an ideal ADC without the use of [[oversampling]].  The input samples are usually stored electronically in [[Binary numeral system|binary]] form within the ADC, so the resolution is usually expressed as the [[audio bit depth]]. In consequence, the number of discrete values available is usually a power of two. For example, an ADC with a resolution of 8 bits can encode an analog input to one in 256 different levels (2<sup>8</sup>&nbsp;=&nbsp;256). The values can represent the ranges from 0 to 255 (i.e. as unsigned integers) or from −128 to 127 (i.e. as signed integer), depending on the application.

Resolution can also be defined electrically, and expressed in [[volt]]s. The change in voltage required to guarantee a change in the output code level is called the [[least significant bit]] (LSB) voltage. The resolution ''Q'' of the ADC is equal to the LSB voltage. The voltage resolution of an ADC is equal to its overall voltage measurement range divided by the number of intervals:

:<math>R = \dfrac{E_\mathrm {FSR}}{2^M - 1},</math>

where ''M'' is the ADC's resolution in bits and ''E''<sub>FSR</sub> is the full-scale voltage range (also called 'span'). ''E''<sub>FSR</sub> is given by

:<math>E_ \mathrm {FSR} = V_\mathrm {RefHi} - V_ \mathrm {RefLow}, \,</math>

where ''V''<sub>RefHi</sub> and ''V''<sub>RefLow</sub> are the upper and lower extremes, respectively, of the voltages that can be coded.

Normally, the number of voltage intervals is given by

:<math>N = 2^M -1, \,</math>

where ''M'' is the ADC's resolution in bits.<ref>{{cite web|url=http://www.ti.com/lit/an/sbaa051a/sbaa051a.pdf |archive-url=https://ghostarchive.org/archive/20221009/http://www.ti.com/lit/an/sbaa051a/sbaa051a.pdf |archive-date=2022-10-09 |url-status=live |title=Principles of Data Acquisition and Conversion |publisher=Texas Instruments |date=April 2015 |access-date=2016-10-18}}</ref>

That is, one voltage interval is assigned in between two consecutive code levels.

Example:
* Coding scheme as in figure 1
* [[Full scale]] measurement range = 0 to 1 volt
* ADC resolution is 3 bits: 2<sup>3</sup> = 8 quantization levels (codes)
* ADC voltage resolution, ''Q'' = 1&nbsp;V / ( 2<sup>3</sup> - 1 ) = 0.143&nbsp;V (intervals)

In many cases, the useful resolution of a converter is limited by the [[signal-to-noise ratio]] (SNR) and other errors in the overall system expressed as an ENOB.

[[File:Frequency spectrum of a sinusoid and its quantization noise floor.gif|thumb|300px|Comparison of quantizing a sinusoid to 64 levels (6 bits) and 256 levels (8 bits).  The additive noise created by 6-bit quantization is 12&nbsp;dB greater than the noise created by 8-bit quantization.  When the spectral distribution is flat, as in this example, the 12&nbsp;dB difference manifests as a measurable difference in the noise floors.]]

====Quantization error====
[[File:Conversion AD DA.png|thumb|Analog to digital conversion as shown with fig. 1 and fig. 2]]

Quantization error is introduced by the [[quantization (signal processing)|quantization]] inherent in an ideal ADC. It is a rounding error between the analog input voltage to the ADC and the output digitized value. The error is nonlinear and signal-dependent. In an ideal ADC, where the quantization error is uniformly distributed between −{{Fraction|1|2}} LSB and +{{Fraction|1|2}} LSB, and the signal has a uniform distribution covering all quantization levels, the [[signal-to-quantization-noise ratio]] (SQNR) is given by

:<math>\mathrm{SQNR} = 20 \log_{10}(2^Q) \approx 6.02 \cdot Q\ \mathrm{dB} \,\!</math><ref>{{cite book|last=Lathi|first=B.P.|title=Modern Digital and Analog Communication Systems|year=1998|publisher=Oxford University Press|edition=3rd}}</ref>

where Q is the number of quantization bits.  For example, for a [[audio bit depth|16-bit]] ADC, the quantization error is 96.3&nbsp;dB below the maximum level.

Quantization error is distributed from DC to the [[Nyquist frequency]]. Consequently, if part of the ADC's bandwidth is not used, as is the case with [[oversampling]], some of the quantization error will occur [[out-of-band]], effectively improving the SQNR for the bandwidth in use.  In an oversampled system, [[noise shaping]] can be used to further increase SQNR by forcing more quantization error out of band.

====Dither====
{{Main|dither}}

In ADCs, performance can usually be improved using [[dither]]. This is a very small amount of random noise (e.g. [[white noise]]), which is added to the input before conversion. Its effect is to randomize the state of the LSB based on the signal. Rather than the signal simply getting cut off altogether at low levels, it extends the effective range of signals that the ADC can convert, at the expense of a slight increase in noise. Dither can only increase the resolution of a sampler. It cannot improve the linearity, and thus accuracy does not necessarily improve.

Quantization distortion in an audio signal of very low level with respect to the bit depth of the ADC is correlated with the signal and sounds distorted and unpleasant. With dithering, the distortion is transformed into noise. The undistorted signal may be recovered accurately by averaging over time. Dithering is also used in integrating systems such as [[electricity meter]]s. Since the values are added together, the dithering produces results that are more exact than the LSB of the analog-to-digital converter.

Dither is often applied when quantizing photographic images to a fewer number of bits per pixel—the image becomes noisier but to the eye looks far more realistic than the quantized image, which otherwise becomes [[colour banding|banded]]. This analogous process may help to visualize the effect of dither on an analog audio signal that is converted to digital.

===Accuracy===
An ADC has several sources of errors. [[Quantization (signal processing)|Quantization]] error and (assuming the ADC is intended to be linear) non-[[linearity]] are intrinsic to any analog-to-digital conversion. These errors are measured in a unit called the [[least significant bit]] (LSB). In the above example of an eight-bit ADC, an error of one LSB is {{Fraction|1|256}} of the full signal range, or about 0.4%.

====Nonlinearity====
All ADCs suffer from nonlinearity errors caused by their physical imperfections, causing their output to deviate from a linear function (or some other function, in the case of a deliberately nonlinear ADC) of their input.{{dubious|Nonlinearity|date=May 2024}} These errors can sometimes be mitigated by [[calibration]], or prevented by testing. Important parameters for linearity are [[integral nonlinearity]] and [[differential nonlinearity]]. These nonlinearities introduce distortion that can reduce the [[signal-to-noise ratio]] performance of the ADC and thus reduce its effective resolution.

===Jitter===<!--[[Sampling (signal processing)]] links here-->
When digitizing a sine wave <math>x(t)=A \sin{(2 \pi f_0 t)}</math>, the use of a non-ideal sampling clock will result in some uncertainty in when samples are recorded. Provided that the actual sampling time uncertainty due to clock [[jitter]] is <math>\Delta t</math>, the error caused by this phenomenon can be estimated as <math>E_{ap} \le |x'(t) \Delta t| \le 2A \pi f_0 \Delta t</math>.  This will result in additional recorded noise that will reduce the [[effective number of bits]] (ENOB) below that predicted by [[quantization error]] alone. The error is zero for DC, small at low frequencies, but significant with signals of high amplitude and high frequency. The effect of jitter on performance can be compared to quantization error: <math>\Delta t < \frac{1}{2^q \pi f_0}</math>, where q is the number of ADC bits.{{citation needed|date=February 2019}}

{| class="wikitable" style="margin: 1em auto;"
|-
! rowspan="2" | Output size <br />(bits) || colspan="7" | Signal Frequency
|-
! 1&nbsp;Hz||1&nbsp;kHz || 10&nbsp;kHz || 1&nbsp;MHz || 10&nbsp;MHz || 100&nbsp;MHz || 1&nbsp;GHz
|- style="text-align:right;" 
|| 8 || style="text-align:right;"| 1,243&nbsp;μs || style="text-align:right;"| 1.24&nbsp;μs || style="text-align:right;"| 124 ns || style="text-align:right;"| 1.24 ns || style="text-align:right;"| 124 ps || style="text-align:right;"| 12.4 ps || style="text-align:right;"| 1.24 ps
|- style="text-align:right;" 
|| 10 || style="text-align:right;"| 311&nbsp;μs || style="text-align:right;"| 311 ns || style="text-align:right;"| 31.1&nbsp;ns || style="text-align:right;"| 311&nbsp;ps || style="text-align:right;"| 31.1&nbsp;ps || style="text-align:right;"| 3.11&nbsp;ps || style="text-align:right;"| 0.31&nbsp;ps
|- style="text-align:right;" 
|| 12 || style="text-align:right;"| 77.7&nbsp;μs || style="text-align:right;"| 77.7&nbsp;ns || style="text-align:right;"| 7.77&nbsp;ns || style="text-align:right;"| 77.7&nbsp;ps || style="text-align:right;"| 7.77&nbsp;ps || style="text-align:right;"| 0.78&nbsp;ps || style="text-align:right;"| 0.08&nbsp;ps (77.7&nbsp;fs)
|- style="text-align:right;" 
|| 14 || style="text-align:right;"| 19.4&nbsp;μs || style="text-align:right;"| 19.4&nbsp;ns || style="text-align:right;"| 1.94&nbsp;ns || style="text-align:right;"| 19.4&nbsp;ps || style="text-align:right;"| 1.94&nbsp;ps || style="text-align:right;"| 0.19&nbsp;ps || style="text-align:right;"| 0.02&nbsp;ps (19.4&nbsp;fs)
|-
| style="text-align:right;"| 16 || style="text-align:right;"| 4.86&nbsp;μs || style="text-align:right;"| 4.86&nbsp;ns || style="text-align:right;"| 486&nbsp;ps || style="text-align:right;"| 4.86&nbsp;ps || style="text-align:right;"| 0.49&nbsp;ps || style="text-align:right;"| 0.05&nbsp;ps (48.5&nbsp;fs)|| style="text-align:center;"| –
|-
| style="text-align:right;"| 18 || style="text-align:right;"| 1.21&nbsp;μs || style="text-align:right;"| 1.21&nbsp;ns || style="text-align:right;"| 121&nbsp;ps || style="text-align:right;"| 1.21&nbsp;ps || style="text-align:right;"| 0.12&nbsp;ps || style="text-align:center;"| – || style="text-align:center;"| –
|-
| style="text-align:right;"| 20 || style="text-align:right;"| 304&nbsp;ns || style="text-align:right;"| 304&nbsp;ps || style="text-align:right;"| 30.4&nbsp;ps || style="text-align:right;"| 0.30&nbsp;ps (303.56&nbsp;fs) || style="text-align:center;"| 0.03&nbsp;ps (30.3&nbsp;fs)|| style="text-align:center;"| – || style="text-align:center;"| –
|-
| style="text-align:right;"| 24 || style="text-align:right;"| 18.9&nbsp;ns || style="text-align:right;"| 18.9&nbsp;ps || style="text-align:right;"| 1.89&nbsp;ps || style="text-align:right;"| 0.019&nbsp;ps (18.9&nbsp;fs) || style="text-align:center;"| - || style="text-align:center;"| – || style="text-align:center;"| –
|-
|}

Clock jitter is caused by [[phase noise]].<ref>{{citation |url=http://www.maxim-ic.com/appnotes.cfm/an_pk/800/ |title=Maxim App 800: Design a Low-Jitter Clock for High-Speed Data Converters |website=maxim-ic.com |date=July 17, 2002}}</ref><ref>{{cite web | title = Jitter effects on Analog to Digital and Digital to Analog Converters | url = http://www.thewelltemperedcomputer.com/Lib/Troisi.pdf | access-date = 19 August 2012}}</ref> The resolution of ADCs with a [[digitization]] bandwidth between 1&nbsp;MHz and 1&nbsp;GHz is limited by jitter.<ref>{{cite journal |doi=10.1016/j.csi.2005.12.005 |title=The effects of aperture jitter and clock jitter in wideband ADCs |last1=Löhning |first1=Michael |last2=Fettweis |first2=Gerhard |year=2007 |journal=Computer Standards & Interfaces Archive |volume =29 |issue=1 |pages=11–18 |citeseerx=10.1.1.3.9217}}</ref> For lower bandwidth conversions such as when sampling audio signals at 44.1&nbsp;kHz, clock jitter has a less significant impact on performance.<ref>{{citation |last1=Redmayne |first1=Derek |last2=Steer |first2=Alison |date=8 December 2008 |url=http://www.eetimes.com/design/automotive-design/4010074/Understanding-the-effect-of-clock-jitter-on-high-speed-ADCs-Part-1-of-2- |title=Understanding the effect of clock jitter on high-speed ADCs |website=eetimes.com}}</ref>

===Sampling rate===
{{Main|Sampling rate}}

An analog signal is [[continuous function|continuous]] in [[time]] and it is necessary to convert this to a flow of digital values. It is therefore required to define the rate at which new digital values are sampled from the analog signal. The rate of new values is called the ''sampling rate'' or ''[[sampling frequency]]'' of the converter. A continuously varying bandlimited signal can be [[Sampling (signal processing)|sampled]] and then the original signal can be reproduced from the discrete-time values by a [[reconstruction filter]]. The Nyquist–Shannon sampling theorem implies that a faithful reproduction of the original signal is only possible if the sampling rate is higher than twice the highest frequency of the signal.

Since a practical ADC cannot make an instantaneous conversion, the input value must necessarily be held constant during the time that the converter performs a conversion (called the ''conversion time''). An input circuit called a [[sample and hold]] performs this task—in most cases by using a [[capacitor]] to store the analog voltage at the input, and using an electronic switch or gate to disconnect the capacitor from the input. Many ADC [[integrated circuit]]s include the sample and hold subsystem internally.

====Aliasing====
{{Main|Aliasing}}
An ADC works by sampling the value of the input at discrete intervals in time. Provided that the input is sampled above the [[Nyquist rate]], defined as twice the highest frequency of interest, then all frequencies in the signal can be reconstructed. If frequencies above half the Nyquist rate are sampled, they are incorrectly detected as lower frequencies, a process referred to as aliasing. Aliasing occurs because instantaneously sampling a function at two or fewer times per cycle results in missed cycles, and therefore the appearance of an incorrectly lower frequency. For example, a 2&nbsp;kHz sine wave being sampled at 1.5&nbsp;kHz would be reconstructed as a 500&nbsp;Hz sine wave.

To avoid aliasing, the input to an ADC must be [[low-pass filter]]ed to remove frequencies above half the sampling rate. This filter is called an ''[[anti-aliasing filter]]'', and is essential for a practical ADC system that is applied to analog signals with higher frequency content. In applications where protection against aliasing is essential, oversampling may be used to greatly reduce or even eliminate it.

Although aliasing in most systems is unwanted, it can be exploited to provide simultaneous down-mixing of a band-limited high-frequency signal (see [[undersampling]] and [[frequency mixer]]). The alias is effectively the lower [[heterodyne]] of the signal frequency and sampling frequency.<ref>{{cite web|title=RF-Sampling and GSPS ADCs – Breakthrough ADCs Revolutionize Radio Architectures|url=http://www.ti.com/lit/sg/snwt001/snwt001.pdf |archive-url=https://ghostarchive.org/archive/20221009/http://www.ti.com/lit/sg/snwt001/snwt001.pdf |archive-date=2022-10-09 |url-status=live|publisher=Texas Instruments|access-date=4 November 2013}}</ref>

====Oversampling====
{{Main|Oversampling}}
For economy, signals are often sampled at the minimum rate required with the result that the quantization error introduced is [[white noise]] spread over the whole [[passband]] of the converter. If a signal is sampled at a rate much higher than the [[Nyquist rate]] and then [[Digital filter|digitally filtered]] to limit it to the signal bandwidth produces the following advantages:
* Oversampling can make it easier to realize analog anti-aliasing filters
* Improved [[audio bit depth]]
* Reduced noise, especially when [[noise shaping]] is employed in addition to oversampling.

Oversampling is typically used in audio frequency ADCs where the required sampling rate (typically 44.1 or 48&nbsp;kHz) is very low compared to the clock speed of typical transistor circuits (>1&nbsp;MHz). In this case, the performance of the ADC can be greatly increased at little or no cost. Furthermore, as any aliased signals are also typically out of band, aliasing can often be eliminated using very low cost filters.

===Relative speed and precision===
The speed of an ADC varies by type. The [[Wilkinson ADC]] is limited by the clock rate which is processable by current digital circuits. For a [[successive-approximation ADC]], the conversion time scales with the logarithm of the resolution, i.e. the number of bits. [[Flash ADC]]s are certainly the fastest type of the three; The conversion is basically performed in a single parallel step.

There is a potential tradeoff between speed and precision. Flash ADCs have drifts and uncertainties associated with the comparator levels results in poor linearity. To a lesser extent, poor linearity can also be an issue for successive-approximation ADCs. Here, nonlinearity arises from accumulating errors from the subtraction processes. Wilkinson ADCs have the best linearity of the three.<ref>{{Harvtxt|Knoll|1989|pp=664–665}}</ref><ref>{{Harvtxt|Nicholson|1974|pp=313–315}}</ref>

===Sliding scale principle===
The sliding scale or randomizing method can be employed to greatly improve the linearity of any type of ADC, but especially flash and successive approximation types.  For any ADC the mapping from input voltage to digital output value is not exactly a [[floor function|floor]] or [[ceiling function]] as it should be. Under normal conditions, a pulse of a particular amplitude is always converted to the same digital value. The problem lies in that the ranges of analog values for the digitized values are not all of the same widths, and the [[differential linearity]] decreases proportionally with the divergence from the average width. The sliding scale principle uses an averaging effect to overcome this phenomenon. A random, but known analog voltage is added to the sampled input voltage. It is then converted to digital form, and the equivalent digital amount is subtracted, thus restoring it to its original value. The advantage is that the conversion has taken place at a random point. The statistical distribution of the final levels is decided by a weighted average over a region of the range of the ADC. This in turn desensitizes it to the width of any specific level.<ref>{{Harvtxt|Knoll|1989|pp=665–666}}</ref><ref>{{Harvtxt|Nicholson|1974|pp=315–316}}</ref>